Integrated circuit devices, commonly known as chips, continue to become more powerful and complex as semiconductor manufacturing technologies have advanced. Whereas early integrated circuit devices included fewer than one hundred transistors, it is now common to integrate hundreds of millions of transistors into a single integrated circuit device. This increased transistor count enables some operations that once required several integrated circuit devices to now be implemented in a single integrated circuit device, often providing greater performance at a lower cost. For example, where previously a data processing system might require separate integrated circuit devices for a microprocessor, a memory, a bus interface, and a memory controller, advances in chip density now permit all of these functions to be integrated into the same integrated circuit device. Such devices are typically known as “systems on a chip” due to the high level of integration they provide.
Increases in chip density have also significantly affected the design methodologies used for integrated circuit chips. Rather than manually laying out individual transistors or logic gates in a design to obtain a desired logic function, typically the functional aspects of the design process are separated from the physical aspects. The functional aspects of a design are typically addressed via a process known as a logic design, which results in the generation of a functional definition of a circuit design, typically defined in a hardware description language (HDL) such as VHDL or Verilog. An HDL representation of a circuit is analogous in many respects to a software program, as the HDL representation generally defines the logic or functions to be performed by a circuit design. Moreover, by separating logic design from physical layout, functions are capable of being defined at a higher level of abstraction. Many design methodologies rely on the concept of hierarchical logic design, where circuits are defined in units and grouped together in one or more parent containers representing collections of units performing higher level functions.
In parallel with the creation of the HDL representation, a physical definition of a circuit design is created typically via a layout process, often referred to as integration, to essentially create a “floor plan” of logic gates and interconnects between the logic gates representing the actual physical arrangement of circuit elements on the manufactured integrated circuit. Automation tools have been developed to utilize predefined cells or blocks of complete circuits to assist with the layout, thus eliminating the need to work with millions of individual logic gates. For example, synthesis tools have been developed to generate Random Logic Macro (RLM) blocks from an HDL representation of a design, whereby an individual laying out a design is merely required to place the RLM blocks and connect them to one another to complete the circuit design. In addition, some designs incorporate blocks from off-the-shelf (OTS) logic blocks, which are reusable from design to design.
Once a physical definition is created, testing and simulation of the design may be performed to identify any potential timing and/or manufacturability issues, and once the design has been determined to meet these requirements, the design may be utilized to manufacture integrated circuits.
As integrated circuits have become more complex, the number of individuals involved in the development and testing processes has increased substantially. Indeed, in many instances the individuals performing the logic design process are completely separate from the integrators who perform the physical design processes, and different individuals may work on different functional units or circuits within a given design. Furthermore, as integrated circuits have become more complex, larger and faster, timing issues become more pronounced, often necessitating the functional definition of a design to be revised after layout has been performed.
With hierarchical logic design, logic paths often span from one physical unit to another. It is a common task to create a timing budget for each unit and initially apportion time between interconnected units so that the individuals or teams designing different units can design those units to meet expected timing constraints for the overall design. However, it is also common for some units to violate the timing budget, sometimes necessitating redesign of those units or other interconnected units to ensure that the overall timing budget of the circuit is met. Given the complexity of modern designs, however, manually reapportioning a timing budget between various units being developed by different individuals or teams can be extremely difficult to coordinate.
Some automated approaches have been utilized to reapportion unit timing budgets such that a unit, in appropriate circumstances, is able to “steal” time from another unit having extra available time, so that timing budgets are reapportioned somewhat automatically. Some approaches, for example, rely on the concept of “slack,” whereby timing analysis is performed on the various units in a design to determine how much those units exceed or fall below their respective timing budgets, then a negotiation algorithm is used to reapportion the timing budgets of the various units. Therefore, whenever one unit exceeds its timing budget (referred to as having “negative slack”), other units that fall below their timing budget (referred to as having “positive slack”) can donate time from their time budget to increase the time budget for the unit with negative slack. Timing budgets are therefore reapportioned in an automated manner, resulting in either confirmation that the overall timing budget for the circuit has been met, or identifying units requiring redesign to meet their respective reapportioned timing budgets.
Conventional slack-based approaches, however, are limited in usefulness whenever timing analysis is unable to find any units with sufficient positive slack available to donate time to units with negative slack. Therefore, a significant need exists in the art for a slack-based timing budget apportionment process that identifies additional opportunities for apportioning slack between different units of a design.